1. Field of the Invention
The present invention relates to a semiconductor device formed by mounting semiconductor elements on both sides of a wiring board having three-dimensional wiring which uses inner via holes.
2. Description of the Related Art
Attempts have been made to develop a semiconductor element in which a plurality of electronic circuits are incorporated in a single semiconductor element (for example IC chip, MIC chip and OEIC chip) in order to make electronic apparatuses having semiconductor elements used therein more compact. In practice, however, it is difficult to make a single semiconductor element having all necessary functions due to limitations related to semiconductor material, production process, design rule and other factors, and it is often necessary to use a plurality of semiconductor elements. In such a case, in order to make the device smaller in size and run at a higher speed, a chip-on-chip configuration is employed in which the semiconductor elements are directly connected with each other by of electrodes as shown in FIG. 19. In the drawing, numeral 1 denotes a first semiconductor element, 2 denotes electrodes formed on the first semiconductor element 1, 3 denotes a second semiconductor element, 4 denotes electrodes formed on the second semiconductor elements, 10 denotes junctions made mainly of an electrically conductive metallic material such as solder, and 11 denotes a cured insulating resin. When such a chip-on-chip configuration is employed, length of wiring between the semiconductor elements can be made shorter, transmission delay of electric signals is reduced, operation speed of the semiconductor device can be made faster and, because the semiconductor elements are mounted in laminated configuration, it is also possible to make the semiconductor device smaller.
If the first semiconductor element 1 and the second semiconductor element 3 are electrically connected via the junctions 10 in such a chip-on-chip configuration as described above, it is necessary to position the electrodes 2, 4 of the semiconductor elements so that they oppose each other. For this reason, general-purpose semiconductor elements cannot be used and it is required to use semiconductor elements which are designed by taking the positions of the electrodes 2, 4 into consideration. Consequently, it is impossible to design the semiconductor elements separately.
Also because the positions of the electrodes 2, 4 of the first and the second semiconductor elements are restricted, it becomes difficult to reduce the size of the semiconductor device in some cases, eventually resulting in lower production yield.
An object of the present invention is to provide a semiconductor device which is capable of operating at a higher speed and is smaller in size by employing general-purpose semiconductor devices without using the chip-on-chip configuration.
Particularly, an object of the present invention is to provide a semiconductor device capable of operating at a higher speed and is smaller in size. This is because the wiring length does not increase even when using semiconductor elements such as a CPU, wherein the electrodes are formed in an array arrangement. Although the examples below utilize a multi-layer wiring board, the objects discussed above can also be achieved by using a wiring board including a single insulation layer.
The present inventors have found that it becomes possible to produce semiconductor devices of smaller size while maintaining a high operating speed of the semiconductor elements by mounting general-purpose semiconductor elements so that they oppose each other via a multi-layer wiring board, in which both sides of the multi-layer wiring board has a three-dimensional wiring layout employing inner via holes for connecting electrodes of the semiconductor elements with each other. Particularly, the semiconductor device can be produced without making the wiring longer even when the semiconductor element has an area array type electrode arrangement by employing the three-dimensional wiring as described above. Thus, the present invention has been completed.
That is, the present invention provides a semiconductor device comprising a multi-layer wiring board having at least first and second semiconductor elements mounted on the respective sides of the multi-layer wiring board. Electrodes of the semiconductor element are connected with each other by the three-dimensional wiring. The multi-layer wiring board is made by laminating insulation layers, which comprise resin-impregnated fiber sheets and circuit pattern layers alternately, and has three-dimensional wiring for electrically connecting the circuit pattern layers provided on both sides of the insulation layer via a plurality of inner via holes that are provided through each of the insulation layers.
The semiconductor device according to the present invention can be made smaller in size in a configuration similar to chip-on-chip configuration by employing the general-purpose semiconductor elements because the semiconductor elements are mounted face down by flip chip bonding via the multi-layer wiring board of thin layers. Particularly because the three-dimensional wiring employing the inner via holes is used in the multi-layer wiring board, the semiconductor elements mounted on both sides of the multi-layer wiring board can be connected by the three-dimensional wiring. Therefore, it is possible to make the wiring shorter compared to a case where a conventional wiring board is used in which lead wires are arranged to run over the substrate surface in two-dimensional wiring.
Consequently, according to the present invention, it becomes possible to achieve a high operating speed of the elements by making the semiconductor device smaller in size so as to prevent a delay in electric signals from occurring by using a reduced wiring length. This is similar to the case of employing the conventional chip-on-chip configuration even when the general-purpose semiconductor elements are used.
Also, because the multi-layer wiring board is disposed between the semiconductor elements, the semiconductor element can be mounted or removed without causing a stress in the other semiconductor elements. Thus, it is possible to prevent the semiconductor elements from being damaged.
It is preferable that projections of one or more semiconductor element mounted on either surface of the multi-layer wiring board in a direction perpendicular to the multi-layer wiring board overlap each other.
When the semiconductor elements are mounted on the respective surfaces of the multi-layer wiring board so that projections thereof in a direction perpendicular to the multi-layer wiring board overlap each other, a potential of the multi-layer wiring board 107 to warp in the perpendicular direction (Z axis direction) can be reduced even in a case in which the insulating substrate constituting the multi-layer wiring board is made of a fiber sheet impregnated with a thermosetting resin which has a low rigidity and is liable to warp.
The present invention also provides a semiconductor device comprising first, second and third semiconductor elements laminated via the multi-layer wiring board. The multi-layer wiring board is bonded to cover the back surface of the second semiconductor element by bending the multi-layer wiring board whereon the first and the second semiconductor elements are mounted at specified positions on either side thereof. The third semiconductor element is mounted by flip chip bonding, so as to oppose the back surface of the second semiconductor element via the multi-layer wiring board.
When the multi-layer wiring board of thin layers is bent and the semiconductor device and the multi-layer wiring board are laminated alternately as described above, the semiconductor device can be made small in size even when a large number of semiconductor elements are mounted.
The present invention also provides a module for mounting semiconductor devices comprising the semiconductor device mounted on a mother multi-layer wiring board having a circuit pattern formed on the surface thereof, with the semiconductor device and the mother multi-layer wiring board being connected by electrical connection means.
By mounting the semiconductor elements on the mother multi-layer wiring board, it becomes possible to form a high-density module. It is also possible to improve the productivity of the module by producing the semiconductor devices in advance and by mounting only qualified semiconductor devices on the mother multi-layer wiring board after testing the semiconductor devices for the quality and reliability.
The electrical connection device is preferably a projecting electrode which is interposed between the multi-layer wiring board of the semiconductor device and the mother multi-layer wiring board by bonding the back surface of the second semiconductor element onto the mother multi-layer wiring board so as to place the semiconductor device on the mother multi-layer wiring board. Therefore, the circuit pattern provided on the multi-layer wiring board and the circuit pattern provided on the mother multi-layer wiring board are connected.
By using the projecting electrode for the electrical connection means, it becomes possible to form the connection means which utilizes the empty space between the multi-layer wiring board of the semiconductor device and the mother multi-layer wiring board. Thus, the module of the semiconductor device is smaller in size.
The electrical connection device preferably establishes an electrical connection between the circuit pattern provided on the multi-layer wiring board of the semiconductor device and the circuit pattern provided on the mother multi-layer wiring board. This connection is established because the back surface of the second semiconductor element is bonded onto the mother multi-layer wiring board, and the multi-layer wiring board of the semiconductor device mounted on the mother multi-layer wiring board is bent.
By bending the multi-layer wiring board of the semiconductor device and thereby forming the connection means, it becomes possible to reduce the number of electrode forming processes and thus reduce the production cost.
The electrical connection device is preferably an electrically conductive supporting body which is electrically connected to the wiring in the multi-layer wiring board of the semiconductor device and is also used to fasten the semiconductor device onto the mother multi-layer wiring board. As a result, an electrical connection is established between the wiring of the multi-layer wiring board of the semiconductor device and the circuit pattern provided on the mother multi-layer wiring board by fastening the semiconductor device onto the mother multi-layer wiring board via the electrically conductive supporting body.
By using the semiconductor device having an electrically conductive supporting body such as metal which is electrically connected to the multi-layer wiring board, it becomes possible to handle the supporting body as if it is a pin of QFP and to mount the device onto the mother multi-layer wiring board or remove the device therefrom easily.
The electrical connection device preferably establishes an electrical connection between the circuit pattern provided on the multi-layer wiring board and the circuit pattern provided on the mother multi-layer wiring board as the semiconductor device is mounted on the mother multi-layer wiring board. Therefore, the multi-layer wiring board, which is bonded to cover the back surface of the second semiconductor element by bending the multi-layer wiring board whereon at least the first and the second semiconductor elements are mounted at specified positions on either side thereof, makes contact with the mother multi-layer wiring board.
By using such a connection device as described above, it becomes possible to make a connection by using the lower region of the mounting surface of the semiconductor element and thereby make the module of the semiconductor device smaller in size.
The present invention also provides a module of the semiconductor device wherein an alternate lamination of the semiconductor device and the multi-layer wiring board is mounted on the mother multi-layer wiring board which has a circuit pattern formed on the surface thereof. Furthermore, the circuit pattern provided on the multi-layer wiring board of the semiconductor device and the circuit pattern provided on the mother multi-layer wiring board are electrically connected to each other.
By using such a module as described above, the semiconductor device can be mounted on the mother multi-layer wiring board with a high density.
The present invention also provides a semiconductor device wherein the electrodes of at least one of the first and the second semiconductor elements are formed in an area array arrangement.
In the multi-layer wiring board according to the present invention, use of the three-dimensional wiring which employs the inner via holes makes it possible to connect between the semiconductor elements mounted on both sides of the multi-layer wiring board in three-dimensional wiring. Consequently, the wiring length can be made shorter compared to a case such as the conventional wiring board in which lead wires are arranged so as to run over the surface of the wiring board in two-dimensional wiring. This configuration is effective for mounting semiconductor elements which have electrodes near the center as well as in the peripheral portions thereof, such as a semiconductor device having electrodes arranged in an area array arrangement.
The present invention also provides a semiconductor device comprising a first semiconductor element having the electrodes arranged in area array arrangement and a second semiconductor element having the electrodes arranged in peripheral arrangement. Both semiconductor elements are mounted face down on the respective surfaces of the multi-layer wiring board by flip chip bonding, wherein the electrodes of both semiconductor elements are connected to each other by the three-dimensional wiring.
As the semiconductor elements are mounted face down by flip chip bonding via the thin layer multi-layer wiring board in the semiconductor device of the present invention, it becomes possible to mount the semiconductor elements by flip chip bonding and make the semiconductor device smaller in size.
In the multi-layer wiring board according to the present invention, use of the three-dimensional wiring comprising inner via holes makes it possible to connect between the semiconductor elements mounted on both sides of the multi-layer wiring board in three-dimensional vertical wiring. Consequently, the wiring can be made shorter compared to a case such as the conventional wiring board in which lead wires are arranged to run over the surface of the wiring board in two-dimensional wiring.
Therefore, the present invention makes it possible to make the semiconductor device smaller in size even when mounting the semiconductor elements having electrodes arranged in area array arrangement. Reduction of the wiring length also makes it possible to increase the operating speed by preventing delay in electrical signals, and to reduce the power consumption by decreasing the resistance of the wiring.
The present invention also provides a semiconductor device wherein the semiconductor element having the electrodes arranged in an area array arrangement is mounted face down on one surface of the multi-layer wiring board by flip chip bonding and electronic components are mounted on the other surface of the multi-layer wiring board. In this arrangement, the electrodes of the semiconductor element and the electrodes of the electronic components are connected with each other by the three-dimensional wiring.
Because the three-dimensional wiring by inner via holes is employed in the multi-layer wiring board of the semiconductor device according to the present invention, the semiconductor element and the electronic components, such as a bypass capacitor mounted on either side of the multi-layer wiring board, can be connected to each other by three-dimensional wiring. In addition, the wiring length can be made shorter compared to a case such as the conventional wiring board in which lead wires are arranged to run over the surface of the wiring board in two-dimensional wiring.
Therefore, noise can be effectively removed during high-speed operation. In particular, when connecting the central electrode of the semiconductor element having electrodes arranged in an area array arrangement and the electronic component, the wiring length can be made far shorter than in the conventional wiring board.
The electronic component is preferably a bypass capacitor. When a bypass capacitor is used as the electronic component, it becomes possible to effectively remove noise due to the bypass capacitor by reducing the wiring length and thereby reducing the noise in the wiring.
As will be clear from the above description, the semiconductor device according to the present invention has semiconductor elements mounted so as to oppose each other via the multi-layer wiring board with the electrodes of the semiconductor elements being connected to each other by means of the three-dimensional wiring of the multi-layer wiring board. Therefore, the elements can be connected with each other regardless of the arrangement of the electrodes of the semiconductor elements, thus making it possible to connect the general-purpose semiconductor elements without modification by a method similar to the chip-on-chip connection and to provide a semiconductor device of smaller size and higher operating speed.
According to the present invention, since a multi-layer wiring board is used instead of the conventional printed circuit board and because connection between the semiconductor elements is made by using the three-dimensional wiring based on the inner via holes which makes it easier to run the lead wires, wiring length can be reduced. Thus, delays are prevented from occurring in the circuit response due to the wiring length, so that the operating speed of the semiconductor device can be increased.
Because the semiconductor elements are not connected directly with each other, it becomes possible to remove or mount any of the semiconductor elements without causing damage to the other semiconductor elements. Also, because the semiconductor device is mounted on the mother multi-layer wiring board, high-density packaging is made possible, thereby contributing to the size reduction of electronic apparatuses.
Further in case the semiconductor element having electrodes of area array arrangement is mounted face down by flip chip bonding, connecting by the multi-layer wiring board 105 having the inner via holes 109 therein makes it possible to reduce the wiring length, increase the operating speed of the semiconductor device, and reduce the power consumption.
In the case of the semiconductor element having electrodes of area array arrangement, in particular, wiring length of the electrode located near the center of the semiconductor element can be greatly reduced compared to a semiconductor device which employs the conventional wiring board.
Also by connecting the bypass capacitors and the semiconductor elements by the three-dimensional wiring comprising the inner via holes, it becomes possible to reduce the wiring length and reduce the noise generated in the semiconductor device.